SH7046 Datasheet, PDF (112/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 6 Interrupt Controller (INTC)
IRQOUT
NMI
IRQ0
IRQ1
IRQ2
IRQ3
UBC
DTC
MTU
CMT
MMT
A/D
SCI
WDT
I/O
Input
control
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
ICR1
ICR2
ISR
Com-
parator
IPR
IPRA to IPRK
Interrupt
request
SR
I3 I2 I1 I0
CPU
DTER
DTC
Module bus
Bus
interface
Legend:
UBC: User break controller
DTC: Data transfer controller
MTU: Multifunction timer unit
CMT: Compare match timer
MMT: Motor management timer
A/D: A/D converter
INTC
SCI:
Serial communications interface
WDT:
Watchdog timer
I/O:
I/O port (Port output controller)
ICR1, ICR2: Interrupt control register
ISR:
IRQ status register
IPRA to IPRK: Interrupt priority level setting registers A to K
SR:
Status register
Figure 6.1 INTC Block Diagram
Rev. 4.00 Dec 05, 2005 page 68 of 564
REJ09B0270-0400