SH7046 Datasheet, PDF (11/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Item
10.7.16 Contention
between
Overflow/Underflow
and Counter Clearing
Figure 10.83
Contention between
Overflow and Counter
Clearing
Page
258
10.7.17 Contention 259
between TCNT Write
and
Overflow/Underflow
Figure 10.84
Contention between
TCNT Write and
Overflow
10.7.22 Notes on
260
Buffer Operation
Settings
10.9.5 Usage Note 302
11.1 Features
303
11.3.3 Reset
308
Control/Status
Register (RSTCSR)
Revision (See Manual for Details)
Figure amended
Pφ
TCNT input
clock
TCNT
H'FFFF
Counter clear
signal
TGF
TCFV
Disabled
Figure amended
Pφ
TCNT write cycle
T1
T2
H'0000
Address
TCNT address
Write signal
TCNT
H'FFFF
TCFV flag
Newly added
TCNT write data
M
Description added
2. To clear bits POE0F, POE1F, POE2F, POE3F, and OSF to
0, read registers ICSR1 and OCSR. Clear bits, which are read
as 1, to 0, and write 1 to the other bits in the registers.
Description replaced
Description amended
RSTCSR is an 8-bit readable/writable register that controls the
generation of the internal reset signal when TCNT overflows .
Rev. 4.00 Dec 05, 2005 page xi of xliv