SH7046 Datasheet, PDF (130/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 6 Interrupt Controller (INTC)
Table 6.3 Interrupt Response Time
Number of States
Item
NMI, Peripheral
Module
IRQ
Remarks
DTC active judgment
0 or 1
1
1 state required for
interrupt signals for which
DTC activation is possible
Interrupt priority judgment 2
3
and comparison with SR
mask bits
Wait for completion of
sequence currently being
executed by CPU
X (≥ 0)
X (≥ 0)
The longest sequence is
for interrupt or address-
error exception processing
(X = 4 + m1 + m2 + m3 +
m4). If an interrupt-
masking instruction follows,
however, the time may be
even longer.
Time from start of
interrupt exception
processing until fetch of
first instruction of
exception service routine
starts
5 + m1 + m2 + m3 5 + m1 + m2 + m3 Performs the saving PC
and SR, and vector
address fetch.
Interrupt
response
time
Total: (7 or 8) + m1 +
m2 + m3+X
Minimum: 10
Maximum: 12 + 2 (m1 + m2
+ m3) + m4
9 + m1 + m2 +
m3 + X
12
13 + 2 (m1 + m2
+ m3) + m4
0.25 0.3 µs at 40 MHz
0.48 µs at 40 MHz^*
Note: * 0.48 µs at 40 MHz is the value in the case that m1 = m2 = m3 = m4 = 1.
m1–m4 are the number of states needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
Rev. 4.00 Dec 05, 2005 page 86 of 564
REJ09B0270-0400