SH7046 Datasheet, PDF (448/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 15 Motor Management Timer (MMT)
15.3.3 Timer Status Register (MMT_TSR)
The timer status register (MMT_TSR) holds status flags. (In this section, the name of this register
is abbreviated to TSR hereafter.)
Initial
Bit Bit Name Value R/W Description
7
TCFD
1
R
Count Direction Flag
Status flag that indicates the count direction of the TCNT
counter.
0: TCNT counts down
1: TCNT counts up
6 to 2 
All 0 R
Reserved
1
TGFN
0
R/(W)^*
These bits are always read as 0 and should only be
written with 0.
Output Compare Flag N
Status flag that indicates a compare match between
TCNT and 2Td (Td: TDDR value).
[Setting condition]
• When TCNT = 2Td
[Clearing condition]
0
TGFM
0
• When 0 is written to TGFN after reading TGFN = 1
R/(W)^* Output Compare Flag M
Status flag that indicates a compare match between
TCNT and the TPDR register.
[Setting condition]
• When TCNT = TPDR
[Clearing condition]
• When 0 is written to TGFM after reading TGFM = 1
Note: * Can only be written with 0 for flag clearing.
Rev. 4.00 Dec 05, 2005 page 404 of 564
REJ09B0270-0400