SH7046 Datasheet, PDF (232/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 10 Multi-Function Timer Pulse Unit (MTU)
TCNT value
TGRB_0
TGRA_0
H'0000
H'0200
H'0450
TGRC_0 H'0200
Transfer
TGRA_0
H'0450
H'0200
H'0520
H'0450
H'0520
Time
TIOCA
Figure 10.16 Example of Buffer Operation (1)
• When TGR is an input capture register
Figure 10.17 shows an operation example in which TGRA has been designated as an input
capture register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling
edges have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon the
occurrence of input capture A, the value previously stored in TGRA is simultaneously
transferred to TGRC.
Rev. 4.00 Dec 05, 2005 page 188 of 564
REJ09B0270-0400