SH7046 Datasheet, PDF (190/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 10 Multi-Function Timer Pulse Unit (MTU)
10.3.3 Timer I/O Control Register (TIOR)
The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU
has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2.
Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is
valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM
mode 2, the output at the point at which the counter is cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4
Initial
Bit Bit Name value R/W Description
7
IOB3
0
R/W I/O Control B0 to B3
6
IOB2
0
R/W Specify the function of TGRB.
5
IOB1
0
R/W See the following tables.
4
IOB0
0
R/W TIORH_0: Table 10.10
TIOR_1: Table 10.14
TIOR_2: Table 10.16
TIORH_3: Table 10.18
TIORH_4: Table 10.22
3
IOA3
0
R/W I/O Control A0 to A3
2
IOA2
0
R/W Specify the function of TGRA.
1
IOA1
0
R/W See the following tables.
0
IOA0
0
R/W TIORH_0: Table 10.11
TIOR_1: Table 10.15
TIOR_2: Table 10.17
TIORH_3: Table 10.19
TIORH_4: Table 10.23
Rev. 4.00 Dec 05, 2005 page 146 of 564
REJ09B0270-0400