SH7046 Datasheet, PDF (156/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 8 Data Transfer Controller (DTC)
8.2.8 DTC Control/Status Register (DTCSR)
The DTCSR is a 16-bit readable/writable register that disables/enables DTC activation by software
and sets the DTC vector addresses for software activation. It also indicates the DTC transfer
status.
Initial
Bit Bit Name Value R/W Description
15

0
R
Reserved
14

13

0
R
These bits have no effect on DTC operation and should
0
R
always be written with 0.
12

0
R
11

0
10
NMIF
0
R
R/(W)^*1 NMI Flag Bit
This bit indicates that an NMI interrupt has occurred.
0: No NMI interrupts
[Clearing condition]
• Write 0 after reading the NMIF bit
1: NMI interrupt has been generated
9
AE
When the NMIF bit is set, DTC transfers are not
allowed even if the DTER bit is set to 1. If, however,
a transfer has already started with the NMIM bit of
the DTMR set to 1, execution will continue until that
transfer ends.
0
R/(W)^*1 Address Error Flag
This bit indicates that an address error by the DTC has
occurred.
0: No address error by the DTC
[Clearing condition]
• Write 0 after reading the AE bit
1: An address error by the DTC occurred
8
SWDTE 0
R/W^*2
When the AE bit is set, DTC transfers are not allowed
even if the DTER bit is set to 1.
DTC Software Activation Enable
Setting this bit to 1 activates DTC.
0: DTC activation by software disabled
1: DTC activation by software enabled
Rev. 4.00 Dec 05, 2005 page 112 of 564
REJ09B0270-0400