SH7046 Datasheet, PDF (454/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 15 Motor Management Timer (MMT)
×2
TGRUU
+
TGRVU
TGRWU ^{(TBR + 2Td)}
Compared during
up-count
TDDR
+
(Td)
TBRU
TBRV
TBRW
(TBR)
TPBR
+
(1/2 period)
TDDR
×2
(Td)
TGRU
TGRV
TGRW
(TBR + Td)
TCNT
TGRUD
TGRVD
TGRWD ^(TBR)
Constantly
compared
Compared during
down-count
(1/2 period + 2Td)
TPDR
TCNT
(2Td)
Compared during Up-count → compare
up-count
match → down-count
Compared during Down-count → compare
down-count
match → up-count
TDDR (Td)
TDCNT
Up-count → compare match → halt
Figure 15.4 Examples of Counter and Register Operations
Initial Settings: In the operating modes, there are five registers that require initialization.
Make the following register settings before setting the operating mode with bits MD1 and MD0 in
the timer mode register (TMDR).
Set the timer period buffer register (TPBR) to 1/2 the PWM carrier period, set dead time Td in the
timer dead time data register (TDDR) (when outputting an ideal waveform, Td = H'0000), and set
{TPBR value + 2Td} in the timer period data register (TPDR).
Rev. 4.00 Dec 05, 2005 page 410 of 564
REJ09B0270-0400