SH7046 Datasheet, PDF (24/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

10.7.7 Contention between Buffer Register Write and Compare Match ........................ 249
10.7.8 Contention between TGR Read and Input Capture.............................................. 251
10.7.9 Contention between TGR Write and Input Capture............................................. 252
10.7.10 Contention between Buffer Register Write and Input Capture ............................ 253
10.7.11 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection ..... 253
10.7.12 Counter Value during Complementary PWM Mode Stop ................................... 255
10.7.13 Buffer Operation Setting in Complementary PWM Mode .................................. 255
10.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag ................. 256
10.7.15 Overflow Flags in Reset Sync PWM Mode ......................................................... 257
10.7.16 Contention between Overflow/Underflow and Counter Clearing........................ 258
10.7.17 Contention between TCNT Write and Overflow/Underflow............................... 259
10.7.18 Cautions on Transition from Normal Operation or PWM Mode 1
to Reset-Synchronous PWM Mode...................................................................... 259
10.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous
PWM Mode.......................................................................................................... 260
10.7.20 Interrupts in Module Standby Mode .................................................................... 260
10.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in Cascade Connection . 260
10.7.22 Notes on Buffer Operation Settings ..................................................................... 260
10.8 MTU Output Pin Initialization .......................................................................................... 261
10.8.1 Operating Modes.................................................................................................. 261
10.8.2 Reset Start Operation ........................................................................................... 261
10.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc.................. 262
10.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error
during Operation, Etc........................................................................................... 263
10.9 Port Output Enable (POE)................................................................................................. 293
10.9.1 Features................................................................................................................ 293
10.9.2 Pin Configuration................................................................................................. 295
10.9.3 Register Configuration......................................................................................... 295
10.9.4 Operation ............................................................................................................. 300
10.9.5 Usage Note........................................................................................................... 302
Section 11 Watchdog Timer............................................................................................. 303
11.1 Features ............................................................................................................................. 303
11.2 Input/Output Pin................................................................................................................ 304
11.3 Register Descriptions ........................................................................................................ 305
11.3.1 Timer Counter (TCNT)........................................................................................ 305
11.3.2 Timer Control/Status Register (TCSR) ................................................................ 305
11.3.3 Reset Control/Status Register (RSTCSR) ............................................................ 308
11.4 Operation .......................................................................................................................... 309
11.4.1 Watchdog Timer Mode ........................................................................................ 309
11.4.2 Interval Timer Mode ............................................................................................ 311
Rev. 4.00 Dec 05, 2005 page xxiv of xliv