SH7046 Datasheet, PDF (47/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Rev. 4.00 Dec 05, 2005 page 3 of 564
REJ09B0270-0400
Figure 1.1 Internal Block Diagram of SH7046
Note: * F-ZTAT version only
: Peripheral address bus (12 bits)
: Peripheral data bus (16 bits)
: Internal address bus (32 bits)
: Internal upper data bus (16 bits)
: Internal lower data bus (16 bits)
Multifunction timer
pulse unit
A/D Watchdog
converter timer
Serial communication
interface
(×2 channels)
Compare match
timer
(×2 channels)
Motor management
timer
(×1 channel)
Bus state controller
User
break*
controller
Interrupt
controller
CPU
RES
WDTOVF
MD3
MD2
MD1
MD0
NMI
EXTAL
XTAL
PLLVcL
PLL
PLLCAP
PLLVss
FWP^*
VcL
VcL
Vcc
Vcc
Vcc
Vss
Vss
Vss
Vss
AVcc
AVcc
AVss
AVss
Data transfer
controller
RAM
Flash ROM/mask ROM
1.2 Internal Block Diagram
Section 1 Overview