SH7046 Datasheet, PDF (78/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 2 CPU
Branch Instructions
Instruction Instruction Code
Operation
BF label 10001011dddddddd If T = 0, disp × 2 + PC → PC;
if T = 1, nop
BF/S label 10001111dddddddd Delayed branch, if T = 0, disp × 2 +
PC → PC; if T = 1, nop
BT label 10001001dddddddd If T = 1, disp × 2 + PC → PC;
if T = 0, nop
BT/S label 10001101dddddddd Delayed branch, if T = 1, disp × 2 +
PC → PC; if T = 0, nop
BRA label 1010dddddddddddd Delayed branch, disp × 2 + PC →
PC
BRAF Rm
0000mmmm00100011 Delayed branch, Rm + PC → PC
BSR label 1011dddddddddddd Delayed branch, PC → PR,
disp × 2 + PC → PC
BSRF Rm
0000mmmm00000011 Delayed branch, PC → PR,
Rm + PC → PC
JMP @Rm 0100mmmm00101011 Delayed branch, Rm → PC
JSR @Rm
0100mmmm00001011 Delayed branch, PC → PR,
Rm → PC
RTS
0000000000001011 Delayed branch, PR → PC
Note: * One state when the program does not branch.
Execution
States
T Bit
3/1^*

3/1^*

3/1^*

2/1^*

2

2

2

2

2

2

2

Rev. 4.00 Dec 05, 2005 page 34 of 564
REJ09B0270-0400