SH7046 Datasheet, PDF (434/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 14 Compare Match Timer (CMT)
Initial
Bit Bit Name Value R/W Description
1
CKS1
0
0
CKS0
0
R/W These bits select the clock input to CMCNT among the
R/W
four internal clocks obtained by dividing the peripheral
clock (Pφ). When the STR bit of CMSTR is set to 1,
CMCNT begins incrementing with the clock selected by
CKS1 and CKS0.
00: Pφ/8
01: Pφ/32
10: Pφ/128
11: Pφ/512
Note: * Only 0 can be written, for flag clearing.
14.2.3 Compare Match Timer Counter_0 and 1 (CMCNT_0, CMCNT_1)
The compare match timer counter (CMCNT) is a 16-bit register used as an up-counter for
generating interrupt requests. The initial value is H’0000.
14.2.4 Compare Match Timer Constant Register_0 and 1 (CMCOR_0, CMCOR_1)
The compare match timer constant register (CMCOR) is a 16-bit register that sets the period for
compare match with CMCNT. The initial value is H'FFFF.
Rev. 4.00 Dec 05, 2005 page 390 of 564
REJ09B0270-0400