SH7046 Datasheet, PDF (445/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 15 Motor Management Timer (MMT)
15.3.1 Timer Mode Register (MMT_TMDR)
The timer mode register (MMT_TMDR) sets the operating mode and selects the PWM output
level. In this section, the name of this register is abbreviated to TMDR hereafter.
Initial
Bit Bit Name Value R/W Description
7

0
R
Reserved
These bits are always read as 0 and should only be
written with 0.
6
CKS2
0
R/W Clock Select 2 to 0
5
CKS1
0
R/W Selects the clock input to MMT.
4
CKS0
0
R/W 000: Pφ
001: Pφ/4
010: Pφ/16
011: Pφ/64
100: Pφ/256
101: Pφ/1024
11x: Setting prohibited.
Note: x “don’t care”.
3
OLSN
0
R/W Output Level Select N
Selects the negative phase output level in the operating
modes.
0: Active level is low
1: Active level is high
2
OLSP
0
R/W Output Level Select P
Selects the positive phase output level in the operating
modes.
0: Active level is low
1: Active level is high
Rev. 4.00 Dec 05, 2005 page 401 of 564
REJ09B0270-0400