SH7046 Datasheet, PDF (30/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

21.4.1 I/O Port Status...................................................................................................... 505
21.4.2 Current Consumption during Oscillation Stabilization Wait Period .................... 505
21.4.3 On-Chip Peripheral Module Interrupt.................................................................. 505
21.4.4 Writing to MSTCR1 and MSTCR2 ..................................................................... 505
21.4.5 DTC Operation in Sleep Mode ............................................................................ 505
Section 22 Electrical Characteristics.............................................................................. 507
22.1 Absolute Maximum Ratings ............................................................................................. 507
22.2 DC Characteristics ............................................................................................................ 508
22.3 AC Characteristics ............................................................................................................ 511
22.3.1 Test Conditions for the AC Characteristics.......................................................... 511
22.3.2 Clock Timing ....................................................................................................... 512
22.3.3 Control Signal Timing ......................................................................................... 514
22.3.4 Multi-Function Timer Pulse Unit (MTU)Timing................................................. 517
22.3.5 I/O Port Timing.................................................................................................... 519
22.3.6 Watchdog Timer (WDT)Timing.......................................................................... 520
22.3.7 Serial Communication Interface (SCI)Timing..................................................... 521
22.3.8 Motor Management Timer (MMT) Timing ......................................................... 523
22.3.9 Port Output Enable (POE) Timing....................................................................... 524
22.3.10 A/D Converter Timing......................................................................................... 525
22.3.11 UBC Trigger Timing............................................................................................ 526
22.4 A/D Converter Characteristics .......................................................................................... 527
22.5 Flash Memory Characteristics........................................................................................... 528
Appendix A Internal I/O Register................................................................................... 531
A.1 Register Addresses (Order of Address)............................................................................. 531
A.2 Register Bits...................................................................................................................... 541
A.3 Register States in Each Operating Mode........................................................................... 551
Appendix B Pin States ....................................................................................................... 557
Appendix C Product Code Lineup.................................................................................. 559
Appendix D Package Dimensions .................................................................................. 560
Index .......................................................................................................................................... 561
Rev. 4.00 Dec 05, 2005 page xxx of xliv