SH7046 Datasheet, PDF (138/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 7 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W
UBAMRH15 to UBM31 to All 0 R/W
UBAMRH 0
UBM16
UBAMRL15 to UBM15 to All 0 R/W
UBAMRL0
UBM0
Description
User Break Address Mask 31 to 16
0: Corresponding UBA bit is included in the break
conditions
1: Corresponding UBA bit is not included in the
break conditions
User Break Address Mask 15 to 0
0: Corresponding UBA bit is included in the break
conditions
1: Corresponding UBA bit is not included in the
break conditions
7.2.3 User Break Bus Cycle Register (UBBR)
The user break bus cycle register (UBBR) is a 16-bit readable/writable register that sets the four
break conditions.
Initial
Bit Bit Name Value R/W
15 to 
8
All 0 R
7
CP1
6
CP0
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
CPU Cycle/DTC Cycle Select 1 and 0
These bits specify break conditions for CPU cycles or
DTC cycles.
00: No user break interrupt occurs
01: Break on CPU cycles
10: Break on DTC cycles
11: Break on both CPU and DTC cycles
Rev. 4.00 Dec 05, 2005 page 94 of 564
REJ09B0270-0400