SH7046 Datasheet, PDF (535/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 20 RAM
Section 20 RAM
The SH7046 Group has an on-chip high-speed static RAM. The on-chip RAM is connected to the
CPU, data transfer controller (DTC) by a 32-bit data bus, enabling 8, 16, or 32-bit width access to
data in the on-chip RAM. Data in the on-chip RAM can always be accessed in one cycle,
providing high-speed access that makes this RAM ideal for use as a program area, stack area, or
data area. The contents of the on-chip RAM are retained in both sleep and software standby
modes.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control
register (SYSCR). For details on the system control register (SYSCR), refer to section 21.2.2,
System Control Register (SYSCR).
Product Type
SH7046
Type of ROM
Flash memory
Mask ROM
RAM Capacity
12 kbytes
4 kbytes
RAM Address
H’FFFFD000 to
H’FFFFFFFF
H’FFFFF000 to
H’FFFFFFFF
20.1 Usage Note
• Module Standby Mode Setting
RAM can be enabled/disabled by the module standby control register. The initial value enables
RAM operation. RAM access is disabled by setting the module standby mode. For details, see
section 21, Power-Down Modes.
Rev. 4.00 Dec 05, 2005 page 491 of 564
REJ09B0270-0400