SH7046 Datasheet, PDF (547/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 21 Power-Down Modes
When clearing software standby mode by the IRQ interrupt, set CKS2 to CKS0 bits so that the
WDT overflow period will be longer than the oscillation stabilization time.
When software standby mode is cleared by the falling edge or both edges of the IRQ pin, the
IRQ pin should be high when the CPU enters software standby mode (when the clock pulse
stops) and should be low when the CPU returns from software standby mode (when the clock
is initiated after the oscillation stabilization). When software standby mode is cleared by the
rising edge of the IRQ pin, the IRQ pin should be low when the CPU enters software standby
mode (when the clock pulse stops) and should be high when the CPU returns from software
standby mode (when the clock is initiated after the oscillation stabilization).
Note: * When the IRQ pin is set to falling-edge detection or both-edge detection, clock
oscillation starts at falling-edge detection. When the IRQ pin is set to rising-edge
detection, clock oscillation starts at rising-edge detection. Do not set the IRQ pin to
low-level detection.
Software Standby Mode Application Example: Figure 21.2 shows an example in which a
transition is made to software standby mode at the falling edge of the NMI pin, and software
standby mode is cleared at a rising edge of the NMI pin.
In this example, when the NMI pin is driven low while the NMI edge select bit (NMIE) in ICR1 is
0 (falling edge detection), an NMI interrupt is accepted. Then, the NMIE bit is set to 1 (rising edge
detection) in the NMI exception service routine, the SSBY bit in SBYCR is set to 1, and a SLEEP
instruction is executed to transfer to software standby mode.
Software standby mode is cleared by driving the NMI pin from low to high.
Rev. 4.00 Dec 05, 2005 page 503 of 564
REJ09B0270-0400