SH7046 Datasheet, PDF (529/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 18 Flash Memory (F-ZTAT Version)
Apply the reset signal while SWE is low to reset the flash memory during its operation: The
reset signal is applied at least 100 µs after the SWE bit has been cleard.
Comply with power-on procedure designated by the programmer maker: When executing an
on-board writing with a programmer, incorrect programming or erasing may occur unless the
power-on procedure designated by the programmer makers is applied.
Wait time: tsswe
Programming/erasing
possible
Wait time: 100 µs
CK
Vcc
FWP
tosc1
tMD^*S3
min 0 µs
min 0 µs
MD3 to MD0*¹
tMDS^*3
RES
SWE bit
SWE
set
SWE
cleared
Period during which flash memory access is prohibited
(tsswe: Wait time after setting SWE bit)*²
Period during which flash memory can be programmed
(Execution of program if flash memory prohibited, and data reads other than verify operations prohibited)
Notes: 1. Except when switching modes, the level of the mode pins (MD3 to MD0) must be fixed until power-off by
pulling the pins up or down.
2. See Section 22.5, Flash Memory Characteristics in Electrical Characteristics.
3. See Section 22.3.3, Control Signal Timing in Electrical Characteristics.
Figure 18.11 Power-On/Off Timing (Boot Mode)
Rev. 4.00 Dec 05, 2005 page 485 of 564
REJ09B0270-0400