SH7046 Datasheet, PDF (533/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 19 Mask ROM
Section 19 Mask ROM
This LSI is available with 64 kbytes or 128 kbytes of on-chip ROM. The on-chip ROM is
connected to the CPU and data transfer controller (DTC) through a 32-bit data bus (figures 19.1
and 19.2). The CPU and DTC can access the on-chip ROM in 8, 16 and 32-bit widths. Data in the
on-chip ROM can always be accessed in one cycle.
Internal data bus (32 bits)
H'00000000
H'00000004
H'00000001
H'00000005
H'00000002
H'00000006
H'00000003
H'00000007
On-chip ROM
H'0000FFFC
H'0000FFFD
H'0000FFFE
H'0000FFFF
Figure 19.1 Mask ROM Block Diagram (SH7148)
Internal data bus (32 bits)
H'00000000
H'00000004
H'00000001
H'00000005
H'00000002
H'00000006
H'00000003
H'00000007
On-chip ROM
H'0001FFFC
H'0001FFFD
H'0001FFFE
H'0001FFFF
Figure 19.2 Mask ROM Block Diagram (SH7048)
Rev. 4.00 Dec 05, 2005 page 489 of 564
REJ09B0270-0400