SH7046 Datasheet, PDF (25/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

11.4.3 Clearing Software Standby Mode ........................................................................ 311
11.4.4 Timing of Setting the Overflow Flag (OVF) ....................................................... 312
11.4.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)........................ 312
11.5 Interrupts ........................................................................................................................... 313
11.6 Usage Notes ...................................................................................................................... 313
11.6.1 Notes on Register Access..................................................................................... 313
11.6.2 TCNT Write and Increment Contention .............................................................. 315
11.6.3 Changing CKS2 to CKS0 Bit Values................................................................... 315
11.6.4 Changing between Watchdog Timer/Interval Timer Modes................................ 315
11.6.5 System Reset by WDTOVF Signal...................................................................... 316
11.6.6 Internal Reset in Watchdog Timer Mode............................................................. 316
11.6.7 Manual Reset in Watchdog Timer Mode ............................................................. 316
11.6.8 Handling of WDTOVF Pin .................................................................................. 316
Section 12 Serial Communication Interface (SCI) .................................................... 317
12.1 Features ............................................................................................................................. 317
12.2 Input/Output Pins .............................................................................................................. 319
12.3 Register Descriptions ........................................................................................................ 319
12.3.1 Receive Shift Register (RSR) .............................................................................. 320
12.3.2 Receive Data Register (RDR) .............................................................................. 320
12.3.3 Transmit Shift Register (TSR) ............................................................................. 320
12.3.4 Transmit Data Register (TDR)............................................................................. 320
12.3.5 Serial Mode Register (SMR)................................................................................ 321
12.3.6 Serial Control Register (SCR).............................................................................. 322
12.3.7 Serial Status Register (SSR) ................................................................................ 324
12.3.8 Serial Direction Control Register (SDCR)........................................................... 327
12.3.9 Bit Rate Register (BRR) ...................................................................................... 327
12.4 Operation in Asynchronous Mode .................................................................................... 340
12.4.1 Data Transfer Format........................................................................................... 340
12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous
Mode .................................................................................................................... 342
12.4.3 Clock.................................................................................................................... 343
12.4.4 SCI initialization (Asynchronous mode).............................................................. 344
12.4.5 Data transmission (Asynchronous mode) ............................................................ 345
12.4.6 Serial data reception (Asynchronous mode) ........................................................ 347
12.5 Multiprocessor Communication Function......................................................................... 351
12.5.1 Multiprocessor Serial Data Transmission ............................................................ 352
12.5.2 Multiprocessor Serial Data Reception ................................................................. 354
12.6 Operation in Clocked Synchronous Mode ........................................................................ 357
12.6.1 Clock.................................................................................................................... 357
12.6.2 SCI initialization (Clocked Synchronous mode).................................................. 357
Rev. 4.00 Dec 05, 2005 page xxv of xliv