SH7046 Datasheet, PDF (18/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Item
22.5 Flash Memory
Characteristics
Table 22.15 Flash
Memory
Characteristics
Page
528,
529
A.2 Register Bits
547,
548
A.3 Register States in 551 to
Each Operating Mode 556
Appendix B Pin
States
Table B.1 Pin States
Appendix D Package
Dimensions
Figure D.1
PRQP0080JD-A
557,
558
560
Revision (See Manual for Details)
Table and notes amended
Item
Reprogramming count
Data retained time
Symbol Min Typ Max
N_WEC
100^*7 10000^*8 —
Unit
Times
N_WEC
— — 100 Times
t_DRP
10^*9 —
—
years
Remarks
Standard
product
Wide
temperature-
range
product
Notes: 7. All characteristics after rewriting are guaranteed up to
this minimum rewriting times
(therefore 1 to min. times).
8. Reference value at 25°C (A rough rewriting target number to
which a rewriting usually functions)
9. Data retention characteristics when rewriting is executed
within the specification values including minimum values.
Table amended
Register
Abbreviation Bit 7
TCSR
OVF
MSTCR1


MSTCR2


MMT_TMDR 
Bit 6
WT/IT


MSTP14
MSTP6
CKS2
Bit 5
TME


MSTP13
MSTP5
CKS1
Bit 4



MSTP12
MSTP4
CKS0
Bit 3

MSTP27
MSTP19


OLSN
Bit 2
CKS2
MSTP26
MSTP18


OLSP
Bit 1
CKS1
MSTP25



MD1
Bit 0
CKS0
MSTP24


MSTP0
MD0
Module
WDT
Power-down
state
MMT
Hardware Standby deleted
Table amended and notes added
Register
Abbreviation
TCSR
TCNT
RSTCSR
Power-On
Reset
Initialized
Initialized
Initialized/
Held^*2
Manual
Reset
Initialized
Initialized
Held
Software
Standby
Initialized/
Held^*1
Initialized
Initialized
Module
Standby



Sleep
Held
Held
Held
Module
WDT
Notes: 1. The bits 7 to 5 (OVF, WT/IT, and TME) in TCSR are
initialized and the bits 2 to 0 (CKS2 to CKS0) are retained.
2. RSTCSR is retained in spite of power-on reset by WDT
overflow.
Table amended
Hardware Standby deleted
Package Code amended and figure replaced
Rev. 4.00 Dec 05, 2005 page xviii of xliv