SH7046 Datasheet, PDF (265/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 10 Multi-Function Timer Pulse Unit (MTU)
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
TCNT_3, 4 value
TCNT_3
TCNT_4
Positive phase
output
Negative phase
output
TDDR
TGR_4
Initial output
Active level
Time
Complementary
PWM mode
(TMDR setting)
TCNT_3, 4 count start
(TSTR setting)
Figure 10.39 Example of Initial Output in Complementary PWM Mode (2)
Complementary PWM Mode PWM Output Generation Method: In complementary PWM
mode, 3-phase output is performed of PWM waveforms with a non-overlap time between the
positive and negative phases. This non-overlap time is called the dead time.
A PWM waveform is generated by output of the output level selected in the timer output control
register in the event of a compare-match between a counter and data register. While TCNTS is
counting, data register and temporary register values are simultaneously compared to create
consecutive PWM pulses from 0 to 100%. The relative timing of on and off compare-match
occurrence may vary, but the compare-match that turns off each phase takes precedence to secure
the dead time and ensure that the positive phase and negative phase on times do not overlap.
Figures 10.40 to 10.42 show examples of waveform generation in complementary PWM mode.
Rev. 4.00 Dec 05, 2005 page 221 of 564
REJ09B0270-0400