SH7046 Datasheet, PDF (356/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 11 Watchdog Timer
11.4.4 Timing of Setting the Overflow Flag (OVF)
In interval timer mode, when TCNT overflows, the OVF bit of TCSR is set to 1 and an interval
timer interrupt (ITI) is simultaneously requested. Figure 11.4 shows this timing.
φ
TCNT
Overflow signal
(internal signal)
H’FF H’00
OVF
Figure 11.4 Timing of Setting OVF
11.4.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
When TCNT overflows in watchdog timer mode, the WOVF bit of RSTCSR is set to 1 and a
WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an
internal reset signal to be generated for the entire chip. Figure 11.5 shows this timing.
φ
TCNT
Overflow signal
(internal signal)
H’FF H’00
WOVF
Figure 11.5 Timing of Setting WOVF
Rev. 4.00 Dec 05, 2005 page 312 of 564
REJ09B0270-0400