SH7046 Datasheet, PDF (304/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 10 Multi-Function Timer Pulse Unit (MTU)
10.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode
When channels 3 and 4 are in complementary PWM mode or reset-synchronous PWM mode, the
PWM waveform output level is set with the OLSP and OLSN bits in the timer output control
register (TOCR). In the case of complementary PWM mode or reset-synchronous PWM mode,
TIOR should be set to H'00.
10.7.20 Interrupts in Module Standby Mode
If module standby mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be
disabled before entering module standby mode.
10.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in Cascade Connection
When cascade-connected timer counters (TCNT_1 and TCNT_2) are operated, cascade values
cannot be captured even if input capture is executed simultaneously with TIOC1A or TIOC1B and
TIOC2A or TIOC2B.
10.7.22 Notes on Buffer Operation Settings
When enabling buffer operation, clear to 0 bit TGIEC or TGIED in the timer interrupt enable
register (TIER) corresponding to the TGRC or TGRD register used as the buffer register.
Rev. 4.00 Dec 05, 2005 page 260 of 564
REJ09B0270-0400