SH7046 Datasheet, PDF (158/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 8 Data Transfer Controller (DTC)
CPU interrupt requests
(those not designated as
DTC activating sources)
IRQ
on-chip
peripheral
Interrupt requests
DTC
DTER
Clear
DTC activation
request
DTC control
Source flag clear
INTC
Figure 8.2 Activating Source Control Block Diagram
8.3.2 Location of Register Information and DTC Vector Table
Figure 8.3 shows the allocation of register information in memory space. The register information
start addresses are designated by DTBR for the upper 16 bits, and the DTC vector table for the
lower 16 bits.
The allocation in order from the register information start address in normal mode is DTMR,
DTCRA, 4 bytes empty (no effect on DTC operation), DTSAR, then DTDAR. In repeat mode it is
DTMR, DTCRA, DTIAR, DTSAR, and DTDAR. In block transfer mode, it is DTMR, DTCRA, 2
bytes empty (no effect on DTC operation), DTCRB, DTSAR, then DTDAR.
Fundamentally, certain RAM areas are designated for addresses storing register information.
Register
information
start address
Memory space
DTMR
DTCRA
DTSAR
DTDAR
Memory space
DTMR
DTCRA
DTIAR
DTSAR
DTDAR
Memory space
DTMR
DTCRA
DTCRB
DTSAR
DTDAR
Register
information
Normal mode
Repeat mode Block transfer mode
Figure 8.3 DTC Register Information Allocation in Memory Space
Rev. 4.00 Dec 05, 2005 page 114 of 564
REJ09B0270-0400