SH7046 Datasheet, PDF (132/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 6 Interrupt Controller (INTC)
Interrupt source
Interrupt source
flag clear (by DTC)
DTER
DTE clear
CPU interrupt request
DTC activation
request
DTECLR
Transfer end
Figure 6.6 Interrupt Control Block Diagram
6.8.1
Handling Interrupt Request Signals as Sources for DTC Activating and CPU
Interrupt
1. For DTC, set the corresponding DTE bits and DISEL bits to 1.
2. Activating sources are applied to the DTC when interrupts occur.
3. When the DTC performs a data transfer, it clears the DTE bit to 0 and sends an interrupt
request to the CPU. The activating source is not cleared.
4. The CPU clears interrupt sources in the interrupt processing routine then confirms the transfer
counter value. When the transfer counter value is not 0, the CPU sets the DTE bit to 1 and
allows the next data transfer. If the transfer counter value = 0, the CPU performs the necessary
end processing in the interrupt processing routine.
6.8.2
Handling Interrupt Request Signals as Source for DTC Activating, but Not CPU
Interrupt
1. For DTC, set the corresponding DTE bits to 1 and clear the DISEL bits to 0.
2. Activating sources are applied to the DTC when interrupts occur.
3. When the DTC performs a data transfer, it clears the activating source. An interrupt request is
not sent to the CPU, because the DTE bit is hold to 1.
4. However, when the transfer counter value = 0 the DTE bit is cleared to 0 and an interrupt
request is sent to the CPU.
5. The CPU performs the necessary end processing in the interrupt processing routine.
Rev. 4.00 Dec 05, 2005 page 88 of 564
REJ09B0270-0400