SH7046 Datasheet, PDF (230/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 10 Multi-Function Timer Pulse Unit (MTU)
Table 10.29 Register Combinations in Buffer Operation
Channel
0
3
4
Timer General Register
TGRA_0
TGRB_0
TGRA_3
TGRB_3
TGRA_4
TGRB_4
Buffer Register
TGRC_0
TGRD_0
TGRC_3
TGRD_3
TGRC_4
TGRD_4
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 10.13.
Compare match signal
Buffer
register
Timer general
register
Comparator
TCNT
Figure 10.13 Compare Match Buffer Operation
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register.
This operation is illustrated in figure 10.14.
Input capture
signal
Buffer
register
Timer general
register
TCNT
Figure 10.14 Input Capture Buffer Operation
Rev. 4.00 Dec 05, 2005 page 186 of 564
REJ09B0270-0400