SH7046 Datasheet, PDF (540/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 21 Power-Down Modes
21.1 Input/Output Pins
Table 21.2 lists the pins relating to power-down mode.
Table 21.2 Pin Configuration
Pin Name
RES
MRES
I/O
Input
Input
Function
Power-on reset input pin
Manual reset input pin
21.2 Register Descriptions
Registers related to power down modes are shown below. For details on register addresses and
register states during each process, refer to appendix A, Internal I/O Register.
• Standby control register (SBYCR)
• System control register (SYSCR)
• Module standby control register 1 (MSTCR1)
• Module standby control register 2 (MSTCR2)
21.2.1 Standby Control Register (SBYCR)
SBYCR is an 8-bit readable/writable register that performs software standby mode control.
Initial
Bit Bit Name Value R/W Description
7
SSBY
0
R/W Software Standby
This bit specifies the transition mode after executing the
SLEEP instruction.
0: Shifts to sleep mode after the SLEEP instruction has
been executed
1: Shifts to software standby mode after the SLEEP
instruction has been executed
This bit cannot be set to 1 when the watchdog timer
(WDT) is operating (when the TME bit in TCSR of the
WDT is set to 1). When transferring to software standby
mode, clear the TME bit to 0, stop the WDT, then set the
SSBY bit to 1.
Rev. 4.00 Dec 05, 2005 page 496 of 564
REJ09B0270-0400