SH7046 Datasheet, PDF (549/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

21.4 Usage Notes
Section 21 Power-Down Modes
21.4.1 I/O Port Status
When a transition is mode to software standby mode while the port high-impedance bit (HIZ) in
SBYCR is 0, I/O port states are retained. Therefore, there is no reduction in current consumption
for the output current when a high-level signal is output.
21.4.2 Current Consumption during Oscillation Stabilization Wait Period
Current consumption increases during the oscillation stabilization wait period.
21.4.3 On-Chip Peripheral Module Interrupt
Relevant interrupt operations cannot be performed in module standby mode. Consequently, if the
CPU enters module standby mode while an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DTC activation source.
Interrupts should therefore be disabled before entering module standby mode.
21.4.4 Writing to MSTCR1 and MSTCR2
MSTCR1 and MSTCR2 should only be written to by the CPU.
21.4.5 DTC Operation in Sleep Mode
In sleep mode, data should not be accessed by the DTC.
Rev. 4.00 Dec 05, 2005 page 505 of 564
REJ09B0270-0400