SH7046 Datasheet, PDF (165/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 8 Data Transfer Controller (DTC)
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt is requested.
Table 8.4 Block Transfer Mode Register Functions
Register
DTMR
DTCRA
DTCRB
DTSAR
DTDAR
Function
Operation mode
control
Transfer count
Block length
Transfer source
address
Transfer destination
address
Values Written Back upon a Transfer Information Write
DTMR
DTCRA – 1
(Not written back)
(DTS = 0) Increment/ decrement/ fixed
(DTS = 1) DTSAR initial value
(DTS = 0) DTDAR initial value
(DTS = 1) Increment/ decrement/ fixed
DTSAR
or
DTDAR
First block
•
•
Block area
•
Transfer
Nth block
DTDAR
or
DTSAR
Figure 8.8 Memory Mapping in Block Transfer Mode
Rev. 4.00 Dec 05, 2005 page 121 of 564
REJ09B0270-0400