SH7046 Datasheet, PDF (433/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 14 Compare Match Timer (CMT)
14.2.2 Compare Match Timer Control/Status Register_0 and 1 (CMCSR_0, CMCSR_1)
The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the
occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the
clock used for incrementation.
Bit
15 to
8
Bit Name

Initial
Value
All 0
7
CMF
0
6
CMIE
0
5 to 2 
All 0
R/W
R
R/(W)^*
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Compare Match Flag
This flag indicates whether or not the CMCNT and
CMCOR values have matched.
0: CMCNT and CMCOR values have not matched
1: CMCNT and CMCOR values have matched
[Clearing conditions]
• Write 0 to CMF after reading 1 from it
• When the DTC is activated by an CMI interrupt and
data is transferred with the DISEL bit in DTMR of
DTC = 0
Compare Match Interrupt Enable
This bit selects whether to enable or disable a compare
match interrupt (CMI) when the CMCNT and CMCOR
values have matched (CMF = 1).
0: Compare match interrupt (CMI) disabled
1: Compare match interrupt (CMI) enabled
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 4.00 Dec 05, 2005 page 389 of 564
REJ09B0270-0400