SH7046 Datasheet, PDF (31/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram of SH7046 ..................................................................... 3
Figure 1.2 SH7046 Pin Arrangement .................................................................................... 4
Section 2 CPU
Figure 2.1 CPU Internal Registers......................................................................................... 10
Figure 2.2 Data Format in Registers...................................................................................... 13
Figure 2.3 Data Formats in Memory ..................................................................................... 13
Figure 2.4 Transitions between Processing States................................................................. 37
Section 3 MCU Operating Modes
Figure 3.1 The Address Map of SH7046 Flash Memory Version......................................... 42
Figure 3.2 The Address Map of SH7048 Mask ROM Version ............................................. 43
Figure 3.3 The Address Map of SH7148 Mask ROM Version ............................................. 44
Section 4 Clock Pulse Generator
Figure 4.1 Block Diagram of the Clock Pulse Generator...................................................... 47
Figure 4.2 Connection of the Crystal Resonator (Example).................................................. 48
Figure 4.3 Crystal Resonator Equivalent Circuit................................................................... 48
Figure 4.4 Example of External Clock Connection............................................................... 49
Figure 4.5 Cautions for Oscillator Circuit System Board Design ......................................... 50
Figure 4.6 Recommended External Circuitry Around the PLL............................................. 50
Section 6 Interrupt Controller (INTC)
Figure 6.1 INTC Block Diagram........................................................................................... 68
Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control ........................................... 78
Figure 6.3 Interrupt Sequence Flowchart .............................................................................. 84
Figure 6.4 Stack after Interrupt Exception Processing .......................................................... 85
Figure 6.5 Example of the Pipeline Operation when an IRQ Interrupt is Accepted ............. 87
Figure 6.6 Interrupt Control Block Diagram ......................................................................... 88
Section 7 User Break Controller (UBC)
Figure 7.1 User Break Controller Block Diagram................................................................. 92
Figure 7.2 Break Condition Determination Method.............................................................. 98
Section 8 Data Transfer Controller (DTC)
Figure 8.1 Block Diagram of DTC........................................................................................ 106
Figure 8.2 Activating Source Control Block Diagram .......................................................... 114
Rev. 4.00 Dec 05, 2005 page xxxi of xliv