SH7046 Datasheet, PDF (348/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 11 Watchdog Timer
ITI (interrupt
request signal)
WDTOVF
Internal reset
signal*
Interrupt
control
Overflow
Clock
Reset
control
Clock
select
φ/2
φ/64
φ/128
φ/256
φ/512
φ/1024
φ/4096
φ/8192
Internal clock
sources
RSTCSR
TCNT
Module bus
TSCR
Bus
interface
Legend:
TCSR: Timer control/status register
TCNT: Timer counter
RSTCSR: Reset control/status register
WDT
Note: * The internal reset signal can be generated by making a register setting.
Power-on reset or manual reset can be selected.
Figure 11.1 Block Diagram of WDT
11.2 Input/Output Pin
Table 11.1 shows the pin configuration.
Table 11.1 Pin Configuration
Pin
Abbreviation I/O
Function
Watchdog timer overflow WDTOVF^*
O
Outputs the counter overflow signal in
watchdog timer mode
Note: * WDTOVF pin should not be pulled-down. If this pin need to be pulled-down, the pull-
down resistance value must be 1 MΩ or higher.
Rev. 4.00 Dec 05, 2005 page 304 of 564
REJ09B0270-0400