SH7046 Datasheet, PDF (469/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 15 Motor Management Timer (MMT)
Notes on Halting TCNT Counter Operation: If TCNT counter operation is halted, a PCM
waveform may be output with dead time (non-overlap time) shorter than the value set in the timer
dead time register (MMT_TDDR) or no dead time at all (value of 0). To prevent this, use one of
the following methods.
(a) Set the CST bit in the timer control register (TCNR) to 1 and do not clear it to 0 after MMT
counter operation starts. If the CST bit is cleared to 0, do not set it to 1 again.
(b) When setting, clearing, and then resetting the CST bit, use the following procedure for clearing
and then resetting.
(1) Use the pin function controller (PFC) to set the PWM output pin as a general input port.
(2) Set the free operation addresses for all the buffer registers (TBRU, TBRV, and TBRW) to
H'0000.
(3) After the specified dead time duration has elapsed, set TCNR to H'00 and clear the CST bit
to 0.
(4) Once again, set the CST bit to 1.
(c) When setting, clearing, and then resetting the CST bit, use the following procedure for clearing
and then resetting.
(1) Clear the CST bit in TCNR to 0 to halt counter operation.
(2) Use the pin function controller to set the PWM output pin as a general input port.
(3) Clear the MSTP14 bit in module standby control register 2 (MSTCR2) to 0 to transition to
module standby mode, and initialize the internal status of MMT.
(4) Immediately set the MSTP14 bit to 1 to transition back from module standby mode.
Reinitialize MMT and the pin.
(5) Set the CST bit in TCNR to 1 to restart counter operation.
Rev. 4.00 Dec 05, 2005 page 425 of 564
REJ09B0270-0400