SH7046 Datasheet, PDF (79/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 2 CPU
System Control Instructions
Instruction
Instruction Code
Operation
CLRT
0000000000001000 0 → T
CLRMAC
0000000000101000 0 → MACH, MACL
LDC Rm,SR
0100mmmm00001110 Rm → SR
LDC Rm,GBR
0100mmmm00011110 Rm → GBR
LDC Rm,VBR
0100mmmm00101110 Rm → VBR
LDC.L @Rm+,SR 0100mmmm00000111 (Rm) → SR, Rm + 4 → Rm
LDC.L @Rm+,GBR 0100mmmm00010111 (Rm) → GBR, Rm + 4 → Rm
LDC.L @Rm+,VBR 0100mmmm00100111 (Rm) → VBR, Rm + 4 → Rm
LDS Rm,MACH 0100mmmm00001010 Rm → MACH
LDS Rm,MACL 0100mmmm00011010 Rm → MACL
LDS Rm,PR
0100mmmm00101010 Rm → PR
LDS.L @Rm+,MACH 0100mmmm00000110 (Rm) → MACH, Rm + 4 →
Rm
LDS.L @Rm+,MACL 0100mmmm00010110 (Rm) → MACL, Rm + 4 → Rm
LDS.L @Rm+,PR 0100mmmm00100110 (Rm) → PR, Rm + 4 → Rm
NOP
0000000000001001 No operation
RTE
0000000000101011 Delayed branch, stack area
→ PC/SR
SETT
0000000000011000 1 → T
SLEEP
0000000000011011 Sleep
STC SR,Rn
0000nnnn00000010 SR → Rn
STC GBR,Rn
0000nnnn00010010 GBR → Rn
STC VBR,Rn
0000nnnn00100010 VBR → Rn
STC.L SR,@–Rn 0100nnnn00000011 Rn – 4 → Rn, SR → (Rn)
STC.L GBR,@–Rn 0100nnnn00010011 Rn – 4 → Rn, GBR → (Rn)
STC.L VBR,@–Rn 0100nnnn00100011 Rn – 4 → Rn, VBR → (Rn)
STS MACH,Rn 0000nnnn00001010 MACH → Rn
STS MACL,Rn 0000nnnn00011010 MACL → Rn
STS PR,Rn
0000nnnn00101010 PR → Rn
STS.L MACH,@–Rn 0100nnnn00000010 Rn – 4 → Rn, MACH → (Rn)
STS.L MACL,@–Rn 0100nnnn00010010 Rn – 4 → Rn, MACL → (Rn)
Execution
States T Bit
1
0
1

1
LSB
1

1

3
LSB
3

3

1

1

1

1

1

1

1

4

1
1
3^*

1

1

1

2

2

2

1

1

1

1

1

Rev. 4.00 Dec 05, 2005 page 35 of 564
REJ09B0270-0400