SH7046 Datasheet, PDF (423/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 13 A/D Converter
13.4.4 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit for each module. The A/D converter
samples the analog input when the A/D conversion start delay time (t_D) has passed after the ADST
bit in ADCR is set to 1, then starts conversion. Figure 13.2 shows the A/D conversion timing.
Table 13.3 shows the A/D conversion time.
As indicated in figure 13.2, the A/D conversion time (t_CONV) includes t_D and the input sampling time
(t_SPL). The length of t_D varies depending on the timing of the write access to ADCR. The total
conversion time therefore varies within the ranges indicated in table 13.3.
In scan mode, the values given in table 13.3 apply to the first conversion time. The values given
in table 13.4 apply to the second and subsequent conversions.
A/D conversion time (t_CONV)
A/D conversion start Analog input
delay time(tD) sampling time(tSPL)
Write cycle
A/D synchronization time
(Up to
(3 states) _{59 states)}
Pφ
Address
Internal write
signal
Analog input
sampling
signal
A/D converter
ADST write timing
Idle state
Sample-and-hold A/D conversion
ADF
End of A/D conversion
Figure 13.2 A/D Conversion Timing
Rev. 4.00 Dec 05, 2005 page 379 of 564
REJ09B0270-0400