SH7046 Datasheet, PDF (435/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

14.3 Operation
Section 14 Compare Match Timer (CMT)
14.3.1 Cyclic Count Operation
When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR
bit of CMSTR is set to 1, CMCNT begins incrementing with the selected clock. When the
CMCNT counter value matches that of the compare match constant register (CMCOR), the
CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the
CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is
requested. The CMCNT counter begins counting up again from H'0000.
Figure 14.2 shows the compare match counter operation.
CMCNT value
CMCOR
Counter cleared by CMCOR
compare match
H'0000
Time
Figure 14.2 Counter Operation
14.3.2 CMCNT Count Timing
One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, Pφ/512) obtained by dividing the peripheral
clock (Pφ) can be selected by the CKS1 and CKS0 bits of CMCSR. Figure 14.3 shows the timing.
Pφ
Internal
clock
CMCNT
input clock
CMCNT
N-1
N
N+1
Figure 14.3 Count Timing
Rev. 4.00 Dec 05, 2005 page 391 of 564
REJ09B0270-0400