SH7046 Datasheet, PDF (542/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 21 Power-Down Modes
21.2.2 System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that performs enables/disables the access to the on-
chip RAM.
Initial
Bit Bit Name Value R/W
7, 6 
All 1 R/W
5 to 1 
All 0 R
0
RAME
1
R/W
Description
Reserved
These bits are always read as 1, and should always be
written with 1.
Reserved
These bits are always read as 0, and should always be
written with 0.
RAM Enable
This bit enables/disables the on-chip RAM.
0: On-chip RAM disabled
1: On-chip RAM enabled
When this bit is cleared to 0, the access to the on-chip
RAM is disabled. In this case, an undefined value is
returned when reading or fetching the data or instruction
from the on-chip RAM, and writing to the on-chip RAM is
ignored.
When RAME is cleared to 0 to disable the on-chip RAM,
an instruction to access the on-chip RAM should not be
set next to the instruction to write to SYSCR. If such an
instruction is set, normal access is not guaranteed.
When RAME is set to 1 to enable the on-chip RAM, an
instruction to read SYSCR should be set next to the
instruction to write to SYSCR. If an instruction to access
the on-chip RAM is set next to the instruction to write to
SYSCR, normal access is not guaranteed.
Rev. 4.00 Dec 05, 2005 page 498 of 564
REJ09B0270-0400