SH7046 Datasheet, PDF (73/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 2 CPU
Instruction
Instruction Code Operation
MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Rm → (R0 + Rn)
MOV.B @(R0,Rm),Rn
0000nnnnmmmm1100 (R0 + Rm) → Sign
extension → Rn
MOV.W @(R0,Rm),Rn
0000nnnnmmmm1101 (R0 + Rm) → Sign
extension → Rn
MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 (R0 + Rm) → Rn
MOV.B R0,@(disp,GBR) 11000000dddddddd R0 → (disp + GBR)
MOV.W R0,@(disp,GBR) 11000001dddddddd R0 → (disp × 2 + GBR)
MOV.L R0,@(disp,GBR) 11000010dddddddd R0 → (disp × 4 + GBR)
MOV.B @(disp,GBR),R0 11000100dddddddd (disp + GBR) → Sign
extension → R0
MOV.W @(disp,GBR),R0 11000101dddddddd (disp × 2 + GBR) → Sign
extension → R0
MOV.L @(disp,GBR),R0 11000110dddddddd (disp × 4 + GBR) → R0
MOVA @(disp,PC),R0 11000111dddddddd disp × 4 + PC → R0
MOVT Rn
0000nnnn00101001 T → Rn
SWAP.B Rm,Rn
0110nnnnmmmm1000 Rm → Swap bottom two
bytes → Rn
SWAP.W Rm,Rn
0110nnnnmmmm1001 Rm → Swap two
consecutive words → Rn
XTRCT Rm,Rn
0010nnnnmmmm1101 Rm: Middle 32 bits of
Rn → Rn
Execution
States T Bit
1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Rev. 4.00 Dec 05, 2005 page 29 of 564
REJ09B0270-0400