SH7046 Datasheet, PDF (352/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 11 Watchdog Timer
11.3.3 Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset
signal when TCNT overflows.
Initial
Bit Bit Name Value R/W Description
7
WOVF 0
R/(W)^* Watchdog Overflow Flag
This bit is set when TCNT overflows in watchdog timer
mode. This bit cannot be set in interval timer mode.
[Setting condition]
• Set when TCNT overflows in watchdog timer mode
[Clearing condition]
• Cleared by reading WOVF, and then writing 0 to
WOVF
6
RSTE
0
R/W Reset Enable
Specifies whether or not a reset signal is generated in the
chip if TCNT overflows in watchdog timer mode.
0: Reset signal is not generated even if TCNT overflows
(Though other peripheral module registers are not
reset, TCNT and TCSR in WDT are reset)
1: Reset signal is generated if TCNT overflows
5
RSTS
0
R/W Reset Select
Selects the type of internal reset generated if TCNT
overflows in watchdog timer mode.
0: Power-on reset
1: Manual reset
4 to 0 
All 1 R
Reserved
These bits are always read as 1, and should only be
written with 1.
Note: * Only 0 can be written, for flag clearing.
Rev. 4.00 Dec 05, 2005 page 308 of 564
REJ09B0270-0400