SH7046 Datasheet, PDF (453/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 15 Motor Management Timer (MMT)
Register Operation: In the operating modes, four buffer registers and ten compare registers are
used.
The registers that are constantly compared with the TCNT counter are TGRU, TGRV, and
TGRW. In addition, TGRUU, TGRVU, TGRWU, and TPDR are compared with TCNT when
TCNT is counting up, and TGRUD, TGRVD, TGRWD are compared with TCNT when TCNT is
counting down. The buffer register for TPDR is TPBR; the buffer register for TGRUU, TGRU,
and TGRUD is TBRU; the buffer register for TGRVU, TGRV, and TGRVD is TBRV; and the
buffer register for TGRWU, TGRW, and TGRWD is TBRW.
To change compare register data, the new data should be written to the corresponding buffer
register. The buffer registers can be read and written to at all times. Data written to the buffer
operation addresses for TPBR and TBRU to TBRW is transferred at the timing specified by bits
MD1 and MD0 in the timer mode register (TMDR). Data written to the free operation addresses
for TBRU to TBRW is transferred immediately.
After data transfer is completed, the relationship between the compare registers and buffer
registers is as follows:
TGRU (TGRV, TGRW) value = TBRU (TBRV, TBRW) value + Td (Td: value set in TDDR)
TGRUU (TGRVU, TGRWU) value = TBRU (TBRV, TBRW) value + 2Td
TGRUD (TGRVD, TGRWD) value = TBRU (TBRV, TBRW) value
TPDR value = TPBR value + 2Td
The values of TBRU to TBRW should always be set in the range H'0000 to H'FFFF – 2Td, and the
value of TPBR should always be set in the range H'0000 to H'FFFF – 4Td.
Figure 15.4 shows examples of counter and register operations.
Rev. 4.00 Dec 05, 2005 page 409 of 564
REJ09B0270-0400