SH7046 Datasheet, PDF (175/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 9 Bus State Controller (BSC)
9.4 Register Descriptions
9.4.1 Bus Control Register 1 (BCR1)
BCR1 is a 16-bit readable/writable register that enables access to the MMT and MTU control
registers.
Initial
Bit Bit Name Value R/W
15

0
R
14
MMTRWE 1
R/W
13
MTURWE 1
R/W
12 to 8 
7 to 4 
3 to 0 
All 0 R
All 0 R
All 1 R
Description
Reserved
This bit is always read as 0 and should always be
written with 0.
MMT Read/Write Enable
This bit enables MMT control register access. For
details, refer to MMT section.
0: MMT control register access is disabled
1: MMT control register access is enabled
MTU Read/Write Enable
This bit enables MTU control register access. For
details, refer to MTU section.
0: MTU control register access is disabled
1: MTU control register access is enabled
Reserved
These bits are always read as 0 and should always be
written with 0.
Reserved
These bits are always read as 0 and should always be
written with 0.
Reserved
These bits are always read as 1 and should always be
written with 1.
9.4.2 RAM Emulation Register (RAMER)
The RAM emulation register (RAMER) is a 16-bit readable/writable register that selects the RAM
area to be used when emulating realtime programming of flash memory. For details, refer to
section 18.5.5, RAM Emulation Register.
Rev. 4.00 Dec 05, 2005 page 131 of 564
REJ09B0270-0400