SH7046 Datasheet, PDF (437/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 14 Compare Match Timer (CMT)
14.4.3 Compare Match Flag Clear Timing
The CMF bit of the CMCSR register is cleared by writing 0 to it after reading 1 or the clearing
signal after the DTC transfer. Figure 14.5 shows the timing when the CMF bit is cleared by the
CPU.
CMCSR write cycle
T1 T2
Pφ
CMF
Figure 14.5 Timing of CMF Clear by the CPU
14.5 Usage Notes
14.5.1 Contention between CMCNT Write and Compare Match
If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the
CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure
14.6 shows the timing.
CMCNT write cycle
T1 T2
Pφ
Address
CMCNT
Internal
write signal
Compare
match signal
CMCNT
N
H' 0000
Figure 14.6 CMCNT Write and Compare Match Contention
Rev. 4.00 Dec 05, 2005 page 393 of 564
REJ09B0270-0400