SH7046 Datasheet, PDF (372/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 12 Serial Communication Interface (SCI)
Table 12.2 Relationships between N Setting in BRR and Effective Bit Rate B₀
Mode
Asynchronous mode
(n = 0)
Asynchronous mode
(n = 1 to 3)
Clocked synchronous
mode (n = 0)
Bit Rate
Pφ × 10⁶
B₀ = _{32 × 22n × (N + 1)}
Pφ × 10⁶
B₀ = _{32 × 22n+1 × (N + 1)}
Pφ × 10⁶
B₀ = _{4 × 22n × (N + 1)}
Error
Error (%) =
B₀
B₁
– 1^ × 100
Error (%) =
B₀
B₁
– 1^ × 100
—
Clocked synchronous
Pφ × 10⁶
mode (n = 1 to 3)
B₀ = _{4 × 22n+1 × (N + 1)}
—
Notes: B₀: Effective bit rate (bit/s) Actual transfer speed according to the register settings
B₁: Logical bit rate (bit/s) Specified transfer speed of the target system
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
Pφ: Peripheral clock operating frequency (MHz)
n : Determined by the SMR settings shown in the following tables.
SMR Setting
CKS1
CKS0
n
0
0
0
0
1
1
1
0
2
1
1
3
Table 12.3 shows sample N settings in BRR in normal asynchronous mode. Table 12.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 12.6 shows sample N
settings in BRR in clocked synchronous mode. For details, refer to section 12.4.2, Receive Data
Sampling Timing and Reception Margin in Asynchronous Mode. Tables 12.5 and 12.7 show the
maximum bit rates with external clock input.
Rev. 4.00 Dec 05, 2005 page 328 of 564
REJ09B0270-0400