SH7046 Datasheet, PDF (465/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 15 Motor Management Timer (MMT)
Status Flag Clearing Timing: A status flag is cleared when the CPU reads 1 from the flag, then 0
is written to it. When the DTC controller is activated, the flag is cleared automatically. Figure
15.13 shows the timing of status flag clearing by the CPU, and figure 15.14 shows the timing of
status flag clearing by the DTC.
Pφ
Address
TSR write cycle
T1 T2
TSR address
Write signal
Status flag
Interrupt
request
signal
Figure 15.13 Timing of Status Flag Clearing by CPU
Pφ
Address
Status flag
DTC
read cycle
T1 T2
DTC
write cycle
T1 T2
Source address Destination address
Interrupt
request signal
Figure 15.14 Timing of Status Flag Clearing by DTC Controller
Rev. 4.00 Dec 05, 2005 page 421 of 564
REJ09B0270-0400