SH7046 Datasheet, PDF (81/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

2.6 Processing States
Section 2 CPU
2.6.1 State Transitions
The CPU has four processing states: reset, exception processing, program execution and power-
down. Figure 2.4 shows the transitions between the states.
From any state
when RES = 0
From any state when
RES = 1 and MRES = 0
Power-on reset state
RES = 0
Manual reset state
When an internal power-on
reset by WDT or internal
manual reset by WDT
occurs
RES = 1
Exception
processing state
RES = 1,
MRES = 1
Exception
processing
source
occurs
Exception
processing
ends
Reset state
NMI interrupt or IRQ
interrupt occurs
Program execution state
SSBY bit cleared
for SLEEP
instruction
SSBY bit set
for SLEEP
instruction
Sleep mode
Software standby mode
Power-down state
Figure 2.4 Transitions between Processing States
Rev. 4.00 Dec 05, 2005 page 37 of 564
REJ09B0270-0400