SH7046 Datasheet, PDF (71/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 2 CPU
Instruction Code Format
Item
Format
Explanation
Instruction
Described in mnemonic.
OP.Sz SRC,DEST
OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement^*2
Instruction
code
Described in MSB ↔
LSB order
mmmm: Source register
nnnn: Destination register
0000: R0
0001: R1
⋅
⋅
⋅
1111: R15
iiii: Immediate data
dddd: Displacement
Outline of the →, ←
Operation
(xx)
Direction of transfer
Memory operand
M/Q/T
Flag bits in the SR
&
Logical AND of each bit
|
Logical OR of each bit
^
Exclusive OR of each bit
~
Logical NOT of each bit
<<n
n-bit left shift
>>n
Execution

states
n-bit right shift
Value when no wait states are inserted^*1
T bit

Value of T bit after instruction is executed.
An em-dash () in the column means no change.
Notes: 1. Instruction execution states: The execution states shown in the table are minimums.
The actual number of states may be increased when (1) contention occurs between
instruction fetches and data access, or (2) when the destination register of the load
instruction (memory → register) equals to the register used by the next instruction.
2. Depending on the operand size, displacement is scaled by ×1, ×2, or ×4. For details,
refer the SH-1/SH-2/SH-DSP Programming Manual.
Rev. 4.00 Dec 05, 2005 page 27 of 564
REJ09B0270-0400