SH7046 Datasheet, PDF (116/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 6 Interrupt Controller (INTC)
Initial
Bit Bit Name Value R/W
13 IRQ1ES1 0
R/W
12 IRQ1ES0 0
R/W
11 IRQ2ES1 0
R/W
10 IRQ2ES0 0
R/W
9
IRQ3ES1 0
R/W
8
IRQ3ES0 0
R/W
7 to 0 
All 0 R
Description
This bit sets the IRQ1 interrupt request edge detection
mode.
00: Interrupt request is detected on falling edge of IRQ1
input
01: Interrupt request is detected on rising edge of IRQ1
input
10: Interrupt request is detected on both of falling and
rising edge of IRQ1 input
11: Cannot be set
This bit sets the IRQ2 interrupt request edge detection
mode.
00: Interrupt request is detected on falling edge of IRQ2
input
01: Interrupt request is detected on rising edge of IRQ2
input
10: Interrupt request is detected on both of falling and
rising edge of IRQ2 input
11: Cannot be set
This bit sets the IRQ3 interrupt request edge detection
mode.
00: Interrupt request is detected on falling edge of IRQ3
input
01: Interrupt request is detected on rising edge of IRQ3
input
10: Interrupt request is detected on both of falling and
rising edge of IRQ3 input
11: Cannot be set
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 4.00 Dec 05, 2005 page 72 of 564
REJ09B0270-0400