SH7046 Datasheet, PDF (33/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

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Reset-Synchronized PWM Mode Operation Example
(When the TOCR’s OLSN = 1 and OLSP = 1).................................................... 206
Block Diagram of Channels 3 and 4 in Complementary PWM Mode................. 209
Example of Complementary PWM Mode Setting Procedure .............................. 211
Complementary PWM Mode Counter Operation ................................................ 213
Example of Complementary PWM Mode Operation........................................... 215
Example of PWM Cycle Updating ...................................................................... 217
Example of Data Update in Complementary PWM Mode................................... 219
Example of Initial Output in Complementary PWM Mode (1) ........................... 220
Example of Initial Output in Complementary PWM Mode (2) ........................... 221
Example of Complementary PWM Mode Waveform Output (1) ........................ 223
Example of Complementary PWM Mode Waveform Output (2) ........................ 223
Example of Complementary PWM Mode Waveform Output (3) ........................ 224
Example of Complementary PWM Mode 0% and 100% Waveform Output (1). 224
Example of Complementary PWM Mode 0% and 100% Waveform Output (2). 225
Example of Complementary PWM Mode 0% and 100% Waveform Output (3). 225
Example of Complementary PWM Mode 0% and 100% Waveform Output (4). 226
Example of Complementary PWM Mode 0% and 100% Waveform Output (5). 226
Example of Toggle Output Waveform Synchronized with PWM Output ........... 227
Counter Clearing Synchronized with Another Channel....................................... 228
Example of Output Phase Switching by External Input (1) ................................. 230
Example of Output Phase Switching by External Input (2) ................................. 230
Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1) 231
Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) 231
Count Timing in Internal Clock Operation .......................................................... 236
Count Timing in External Clock Operation ......................................................... 236
Count Timing in External Clock Operation (Phase Counting Mode) .................. 237
Output Compare Output Timing (Normal Mode/PWM Mode) ........................... 237
Output Compare Output Timing (Complementary PWM Mode/
Reset Synchronous PWM Mode)......................................................................... 238
Input Capture Input Signal Timing ...................................................................... 238
Counter Clear Timing (Compare Match)............................................................. 239
Counter Clear Timing (Input Capture)................................................................. 239
Buffer Operation Timing (Compare Match) ........................................................ 240
Buffer Operation Timing (Input Capture)............................................................ 240
TGI Interrupt Timing (Compare Match).............................................................. 241
TGI Interrupt Timing (Input Capture).................................................................. 242
TCIV Interrupt Setting Timing ............................................................................ 243
TCIU Interrupt Setting Timing ............................................................................ 243
Timing for Status Flag Clearing by the CPU ....................................................... 244
Timing for Status Flag Clearing by DTC Activation ........................................... 244
Rev. 4.00 Dec 05, 2005 page xxxiii of xliv