SH7046 Datasheet, PDF (276/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 10 Multi-Function Timer Pulse Unit (MTU)
A/D Conversion Start Request Setting: In complementary PWM mode, an A/D conversion start
request can be set using a TGRA_3 compare-match or a compare-match on a channel other than
channels 3 and 4.
When start requests using a TGRA_3 compare-match are set, A/D conversion can be started at the
center of the PWM pulse.
A/D conversion start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable
register (TIER).
Complementary PWM Mode Output Protection Function
Complementary PWM mode output has the following protection functions.
• Register and counter miswrite prevention function
With the exception of the buffer registers, which can be rewritten at any time, access by the
CPU can be enabled or disabled for the mode registers, control registers, compare registers,
and counters used in complementary PWM mode by means of bit 13 in the bus controller’s bus
control register 1 (BCR1). Some registers in channels 3 and 4 concerned are listed below: total
21 registers of TCR_3 and TCR_4; TMDR_3 and TMDR_4; TIORH_3 and TIORH_4;
TIORL_3 and TIORL_4; TIER_3 and TIER_4; TCNT_3 and TCNT_4; TGRA_3 and
TGRA_4; TGRB_3 and TGRB_4; TOER; TOCR; TGCR; TCDR; and TDDR. This function
enables the CPU to prevent miswriting due to the CPU runaway by disabling CPU access to
the mode registers, control register, and counters. In access disabled state, an undefined value
is read from the registers concerned, and cannot be modified.
• Halting of PWM output by external signal
The 6-phase PWM output pins can be set automatically to the high-impedance state by
inputting specified external signals. There are four external signal input pins.
See section 10.9, Port Output Enable (POE), for details.
• Halting of PWM output when oscillator is stopped
If it is detected that the clock input to this LSI has stopped, the 6-phase PWM output pins
automatically go to the high-impedance state. The pin states are not guaranteed when the clock
is restarted.
See section 4.2, Function for Detecting the Oscillator Halt.
Rev. 4.00 Dec 05, 2005 page 232 of 564
REJ09B0270-0400